1. Field of the Invention
The present invention relates to the field of computers and computer processors, and more particularly to analog-to-digital converters (ADCs).
2. Description of the Background Art
An analog-to-digital converter (ADC) is an electronic circuit that converts continuous signals to discrete digital numbers. Typically, an ADC is an electronic device that converts an input analog voltage to a digital number.
The analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter, and is typically reported as the number of samples per second (sps).
A continuously varying bandlimited signal can be sampled at intervals of time T, the sampling time, and measured and stored. The original signal can then be exactly reproduced from the discrete-time values by an interpolation formula. However, this reproduction is only possible if the sampling rate is higher than twice the highest frequency of the signal. This is sometimes referred to as the Shannon-Nyquist sampling theorem. Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time, called the conversion time, within which the converter performs a conversion.
It is often desirable to be able to sample analog signals in an integrated circuit (IC) at very high frequencies, for example in the range of several gigahertz (GHz). However, certain types of ICs are made with older semiconductor manufacturing and material technology that is capable of sampling signals only at lower frequencies, for example in the range of <1-2 GHz.
FIG. 1 is a diagrammatic representation of an example of an analog-to-digital (A-to-D) sampling system 100 as is currently known in the art. Embedded in chip 101 is the A-to-D block 102. A-to-D block 102 has a data output 105, typically, but not necessarily a parallel bus, and a sampling frequency control 104, which is used to sample input signal 103. The highest frequency component of the input component is fi, and the sampling frequency fs must be at least twice the frequency of fi, preferably 2.2 times the frequency of fi for sampling that supports functions such as Fourier Transformations (FT) or Fast Fourier Transformations (FFT), etc. Therefore, if the desired input frequency fi is in the 10 GHz range, the chip must be able to clock the sampling frequency fs at approximately 20-22 GHz, based on the Nyquist Frequency. Building a chip with such a high sampling frequency is more costly, and the architecture of such chips does not permit embedding of large data functions such as CPUs, memory, etc. in such a chip.
Several analog-to-digital conversion methods are known. FIG. 1A is a schematic representation of a sample and hold circuit diagram for an ADC, which is also called a track and hold circuit. When the sample and hold switch 110 is open, the last instantaneous value of the input voltage is held on the sample and hold capacitor 111. When the sample and hold switch 110 is closed, the circuit is in track mode. Buffers 112 on the input and output isolate the sample and hold capacitor 111. A sample and hold ADC is simple and reliable, but is limited in its sampling frequency rate and it has a high error probability.
A second analog-to-digital conversion method is that which utilizes a phase detector ADC. A phase detector generates a voltage signal which represents the difference in phase between two signal inputs. When the two compared signals are completely in phase, the two equal inputs to an XOR gate will output a constant level of zero. With a one degree phase difference, the XOR gate will output a 1 for the duration of the signals being different ( 1/360th of the cycle). When the signals are 180 degrees apart, the XOR gate puts out a steady 1 signal. Integration of the output signal results in an analog voltage proportional to the phase difference. A phase detector contains a number of XOR gates that simultaneously measure a number of phase differences of the input signal. This has the advantage of being a fast acting device, but has the disadvantage of being a large power consumption device.
A third analog-to-digital conversion method is that which utilizes a flash ADC, which is also called a parallel ADC. FIG. 1B is a schematic representation of a flash ADC circuit diagram. A flash ADC is formed of a series of comparators 120, where each comparator 120 compares the input signal to a unique reference voltage. The comparator 120 outputs connect to the inputs of a priority encoder circuit 121, which then produces a binary output 122. As the analog input voltage exceeds the reference voltage at each comparator 120, the comparator 120 outputs will sequentially saturate to a high state. The priority encoder 121 generates a binary number based on the highest order active input, ignoring all other active inputs. The flash ADC is efficient in terms of speed, but contains a large number of components. For example, a three-bit flash ADC requires eight comparators, a four-bit version requires 16 comparators, and an eight-bit version requires 256 comparators.
A fourth analog-to-digital conversion method is a successive approximation ADC, schematically shown in FIG. 1C. The successive approximation ADC uses a successive approximation register (SAR) 130 as a sequence counter. This SAR 130 counts by trying all values of bits starting with the most significant bit (MSB) and finishing at the least significant bit (LSB). Throughout the count process, the SAR 130 monitors the comparator's output to see if the binary count is less than or greater than the analog signal input, and then adjusts the bit values accordingly. Different values of bits are tried from MSB to LSB to get a binary number that equals the original decimal number. The digital-to-analog converter (DAC) 131 output converges on the analog signal input much faster than with a regular sequence counter. The stoichastic renormalization group (SRG) 132 acts as a decimal to binary converter. The successive approximation ADC is a faster device, but has the disadvantages of high power consumption and a large number of components.
Various approaches have been taken to find an economical system that can sample high frequency input rates. In an article entitled, Design of a High-Performance Analog-to-Digital Converter, by Kevin Nary, published in CSD Magazine in October 1998, Nary discloses a folding and interpolating 8-bit 2-Gsps ADC. The number of comparators required for a 4-bit ADC is reduced from fifteen to six when switching from a flash to a folding architecture. This ADC increases the analog bandwidth and the maximum sample rate and consumes less power than a flash architecture ADC. One method of achieving a folding function uses cross-coupled, differential amplifiers, where a single fold is achieved with two cross-coupled, differential amplifiers. By adding more resistors and differential pairs, the number of folds may be increased. Nary reported results of a 2 GHz sampling frequency with 98 MHz input frequency.
Another approach has been disclosed in an article entitled, Capturing Data from Gigasample Analog-to-Digital Converters, by Ian King, published in I/O Magazine in January 2006, which discloses a method of de-multiplexing the digital output. For a 1.5 GHz sample rate, the conversion data will be output synchronous to a 750 MHz clock, where the data is presented to the outputs on both the rising and falling edges of the clock. Two latches are then used, wherein one latch is clocked on the rising edge of the phase-locked data clock and a second latch is clocked using a signal that is 180 degrees out of phase. This reduces the output to 375 MHz. After latching the incoming data, the clock domain is shifted using an intermediate set of latches so that all of the data can be clocked into a memory array on the same clock edge, which de-multiplexes the data rate to 187.5 MHz. A single-channel device can be put into a dual-edge sampling mode to increase the sampling speed from 1.5 Gsps to 3.0 Gsps, which increases the number of output data bits from 8 to 16. A system and method are clearly needed in which much higher sampling frequencies than 2-3 GHz can be converted.